Xilinx Design Summary

DEMO Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	340	11,776	2%
Number of 4 input LUTs	199	11,776	1%
Logic Distribution
Number of occupied Slices	344	5,888	5%
Number of Slices containing only related logic	344	344	100%
Number of Slices containing unrelated logic	0	344	0%
Total Number of 4 input LUTs	406	11,776	3%
Number used as logic	199
Number used as a route-thru	127
Number used as Shift registers	80
Number of bonded IOBs	13	372	3%
IOB Flip Flops	1
Number of GCLKs	4	24	16%
Number of DCMs	1	8	12%
Number of BSCANs	1	1	100%
Number of BSCAN_SPARTAN3As	1	1	100%
Number of RAMB16BWEs	1	20	5%
Number of RPM macros	13
Total equivalent gate count for design	17,194
Additional JTAG gate count for IOBs	624

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met