Device Usage Page (device_usage_statistics.html)

This HTML page displays the device usage statistics that will be sent to Xilinx. The file also contains predefined XML tags used to simplify processing.
 
Please verify the contents are okay to send to Xilinx!
 

 
Software Version and Target Device
Product Version: ISE:10.1.01 (Foundation) Target Family: spartan3a
OS Platform: NT Target Device: xc3s700a
Project ID (random number) 27491.16474.4 Target Package: fg484
Registration ID 18D2AJDJTK7PWTKBPEGW2J2JF Target Speed: -5
Date Generated 木 5 15 19:57:36 2008
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Counters=4
  • 22-bit up counter=1
  • 28-bit up counter=2
  • 4-bit up counter=1
Comparators=3
  • 22-bit comparator greatequal=1
  • 28-bit comparator greatequal=2
Registers=15
  • Flip-Flops=15
Multiplexers=1
  • 8-bit 4-to-1 multiplexer=1
MiscellaneousStatistics
  • AGG_BONDED_IO=13
  • AGG_IO=13
  • AGG_SLICE=365
  • NUM_4_INPUT_LUT=484
  • NUM_BONDED_IBUF=5
  • NUM_BONDED_IOB=8
  • NUM_BSCAN=1
  • NUM_BUFGMUX=4
  • NUM_CARRY_SKIP=3
  • NUM_CYMUX=164
  • NUM_DCM=1
  • NUM_IOB_FF=1
  • NUM_LUT_RT=145
  • NUM_RAMB16BWE=1
  • NUM_RPM=13
  • NUM_SHIFT=80
  • NUM_SLICEL=300
  • NUM_SLICEM=65
  • NUM_SLICE_FF=340
  • NUM_XOR=128
NetStatistics
  • NumNets_Active=726
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=23
  • NumNodesOfType_Active_BRAMDUMMY=16
  • NumNodesOfType_Active_CLKPIN=258
  • NumNodesOfType_Active_CNTRLPIN=267
  • NumNodesOfType_Active_DOUBLE=1108
  • NumNodesOfType_Active_DUMMY=1161
  • NumNodesOfType_Active_DUMMYBANK=17
  • NumNodesOfType_Active_DUMMYESC=6
  • NumNodesOfType_Active_GLOBAL=104
  • NumNodesOfType_Active_HFULLHEX=5
  • NumNodesOfType_Active_HLONG=3
  • NumNodesOfType_Active_HUNIHEX=62
  • NumNodesOfType_Active_INPUT=1630
  • NumNodesOfType_Active_IOBOUTPUT=6
  • NumNodesOfType_Active_OMUX=719
  • NumNodesOfType_Active_OUTPUT=709
  • NumNodesOfType_Active_PREBXBY=528
  • NumNodesOfType_Active_VFULLHEX=69
  • NumNodesOfType_Active_VLONG=13
  • NumNodesOfType_Active_VUNIHEX=99
  • NumNodesOfType_Vcc_BRAMDUMMY=1
  • NumNodesOfType_Vcc_CNTRLPIN=9
  • NumNodesOfType_Vcc_DUMMY=63
  • NumNodesOfType_Vcc_INPUT=80
  • NumNodesOfType_Vcc_PREBXBY=16
  • NumNodesOfType_Vcc_VCCOUT=26
SiteSummary
  • BSCAN=1
  • BSCAN_BSCAN_BLACKBOX=1
  • BUFGMUX=4
  • BUFGMUX_GCLKMUX=4
  • BUFGMUX_GCLK_BUFFER=4
  • DCM=1
  • DCM_DCM=1
  • IBUF=5
  • IBUF_DELAY_ADJ_BBOX=5
  • IBUF_IFF1=1
  • IBUF_INBUF=5
  • IBUF_PAD=5
  • IOB=8
  • IOB_OUTBUF=8
  • IOB_PAD=8
  • RAMB16BWE=1
  • RAMB16BWE_RAMB16BWE=1
  • SLICEL=300
  • SLICEL_C1VDD=16
  • SLICEL_C2VDD=14
  • SLICEL_CYMUXF=78
  • SLICEL_CYMUXG=70
  • SLICEL_F=187
  • SLICEL_F5MUX=32
  • SLICEL_F6MUX=13
  • SLICEL_FFX=145
  • SLICEL_FFY=179
  • SLICEL_G=191
  • SLICEL_GNDF=62
  • SLICEL_GNDG=56
  • SLICEL_XORF=61
  • SLICEL_XORG=62
  • SLICEM=65
  • SLICEM_CYMUXF=8
  • SLICEM_CYMUXG=8
  • SLICEM_F=46
  • SLICEM_F5MUX=27
  • SLICEM_F6MUX=16
  • SLICEM_FFX=9
  • SLICEM_FFY=7
  • SLICEM_FMC15_BLACKBOX=23
  • SLICEM_G=60
  • SLICEM_GMC15_BLACKBOX=42
  • SLICEM_GNDF=8
  • SLICEM_GNDG=5
  • SLICEM_VDDG=3
  • SLICEM_WSGEN=49
  • SLICEM_XORF=5
  • SLICEM_YBUSED=17
 
Configuration Data
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:4]
DCM_DCM
  • CLKDV_DIVIDE=[4:1]
  • CLKOUT_PHASE_SHIFT=[NONE:1]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[8:1]
  • DFS_FREQUENCY_MODE=[LOW:1]
  • DLL_FREQUENCY_MODE=[LOW:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • FACTORY_JF1=[0XC0:1]
  • FACTORY_JF2=[0X80:1]
IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:5]
  • IBUF_DELAY_VALUE=[DLY0:5]
  • IFD_DELAY_VALUE=[DLY0:4] [DLY5:1]
IBUF_IFF1
  • IFF1_INIT_ATTR=[INIT1:1]
  • LATCH_OR_FF=[FF:1]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:5]
IOB_OUTBUF
  • SUSPEND=[3STATE:8]
IOB_PAD
  • DRIVEATTRBOX=[12:8]
  • IOATTRBOX=[LVCMOS25:8]
  • SLEW=[SLOW:8]
RAMB16BWE_RAMB16BWE
  • DATA_WIDTH_A=[1:1]
  • DATA_WIDTH_B=[36:1]
  • WRITE_MODE_A=[WRITE_FIRST:1]
  • WRITE_MODE_B=[WRITE_FIRST:1]
SLICEL_FFX
  • FFX_INIT_ATTR=[INIT0:128] [INIT1:17]
  • FFX_SR_ATTR=[SRLOW:136] [SRHIGH:9]
  • LATCH_OR_FF=[FF:145]
  • SYNC_ATTR=[ASYNC:46] [SYNC:99]
SLICEL_FFY
  • FFY_INIT_ATTR=[INIT0:165] [INIT1:14]
  • FFY_SR_ATTR=[SRLOW:166] [SRHIGH:13]
  • LATCH_OR_FF=[FF:179]
  • SYNC_ATTR=[ASYNC:59] [SYNC:120]
SLICEM_F
  • F_ATTR=[SHIFT_REG:31]
  • LUT_OR_MEM=[LUT:15] [RAM:31]
SLICEM_FFX
  • FFX_INIT_ATTR=[INIT0:7] [INIT1:2]
  • FFX_SR_ATTR=[SRLOW:7] [SRHIGH:2]
  • LATCH_OR_FF=[FF:9]
  • SYNC_ATTR=[ASYNC:4] [SYNC:5]
SLICEM_FFY
  • FFY_INIT_ATTR=[INIT0:7]
  • FFY_SR_ATTR=[SRLOW:7]
  • LATCH_OR_FF=[FF:7]
  • SYNC_ATTR=[ASYNC:6] [SYNC:1]
SLICEM_G
  • G_ATTR=[SHIFT_REG:49]
  • LUT_OR_MEM=[LUT:11] [RAM:49]
SLICEM_WSGEN
  • SYNC_ATTR=[ASYNC:5]
 
Pin Data
BSCAN
  • DRCK1=1
  • SEL1=1
  • SHIFT=1
  • TDI=1
  • TDO1=1
  • TDO2=1
  • UPDATE=1
BSCAN_BSCAN_BLACKBOX
  • DRCK1=1
  • SEL1=1
  • SHIFT=1
  • TDI=1
  • TDO1=1
  • TDO2=1
  • UPDATE=1
BUFGMUX
  • I0=4
  • O=4
  • S=4
BUFGMUX_GCLKMUX
  • I0=4
  • OUT=4
  • S=4
BUFGMUX_GCLK_BUFFER
  • IN=4
  • OUT=4
DCM
  • CLK0=1
  • CLKDV=1
  • CLKFB=1
  • CLKIN=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
DCM_DCM
  • CLK0=1
  • CLKDV=1
  • CLKFB=1
  • CLKIN=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
IBUF
  • I=5
  • ICLK1=1
  • IQ1=1
  • PAD=5
IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=5
  • IFD_OUT=1
  • SEL_IN=5
IBUF_IFF1
  • CK=1
  • D=1
  • Q=1
IBUF_INBUF
  • IN=5
  • OUT=5
IBUF_PAD
  • PAD=5
IOB
  • O1=8
  • PAD=8
IOB_OUTBUF
  • IN=8
  • OUT=8
IOB_PAD
  • PAD=8
RAMB16BWE
  • ADDRA0=1
  • ADDRA1=1
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA2=1
  • ADDRA3=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • ADDRB10=1
  • ADDRB11=1
  • ADDRB12=1
  • ADDRB13=1
  • ADDRB5=1
  • ADDRB6=1
  • ADDRB7=1
  • ADDRB8=1
  • ADDRB9=1
  • CLKA=1
  • CLKB=1
  • DIA0=1
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB16=1
  • DIB17=1
  • DIB18=1
  • DIB19=1
  • DIB2=1
  • DIB20=1
  • DIB21=1
  • DIB22=1
  • DIB23=1
  • DIB24=1
  • DIB25=1
  • DIB26=1
  • DIB27=1
  • DIB28=1
  • DIB29=1
  • DIB3=1
  • DIB30=1
  • DIB31=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPB0=1
  • DIPB1=1
  • DIPB2=1
  • DIPB3=1
  • DOA0=1
  • ENA=1
  • ENB=1
  • SSRA=1
  • SSRB=1
  • WEA0=1
  • WEA1=1
  • WEA2=1
  • WEA3=1
  • WEB0=1
  • WEB1=1
  • WEB2=1
  • WEB3=1
RAMB16BWE_RAMB16BWE
  • ADDRA0=1
  • ADDRA1=1
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA2=1
  • ADDRA3=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • ADDRB10=1
  • ADDRB11=1
  • ADDRB12=1
  • ADDRB13=1
  • ADDRB5=1
  • ADDRB6=1
  • ADDRB7=1
  • ADDRB8=1
  • ADDRB9=1
  • CLKA=1
  • CLKB=1
  • DIA0=1
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB16=1
  • DIB17=1
  • DIB18=1
  • DIB19=1
  • DIB2=1
  • DIB20=1
  • DIB21=1
  • DIB22=1
  • DIB23=1
  • DIB24=1
  • DIB25=1
  • DIB26=1
  • DIB27=1
  • DIB28=1
  • DIB29=1
  • DIB3=1
  • DIB30=1
  • DIB31=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPB0=1
  • DIPB1=1
  • DIPB2=1
  • DIPB3=1
  • DOA0=1
  • ENA=1
  • ENB=1
  • SSRA=1
  • SSRB=1
  • WEA0=1
  • WEA1=1
  • WEA2=1
  • WEA3=1
  • WEB0=1
  • WEB1=1
  • WEB2=1
  • WEB3=1
SLICEL
  • BX=105
  • BY=113
  • CE=55
  • CIN=68
  • CLK=197
  • COUT=70
  • F1=183
  • F2=106
  • F3=75
  • F4=44
  • F5=22
  • FX=5
  • FXINA=13
  • FXINB=13
  • G1=189
  • G2=127
  • G3=94
  • G4=49
  • SR=159
  • X=73
  • XB=2
  • XQ=145
  • Y=72
  • YQ=179
SLICEL_C1VDD
  • 1=16
SLICEL_C2VDD
  • 1=14
SLICEL_CYMUXF
  • 0=78
  • 1=78
  • OUT=78
  • S0=78
SLICEL_CYMUXG
  • 0=70
  • 1=70
  • OUT=70
  • S0=70
SLICEL_F
  • A1=183
  • A2=106
  • A3=75
  • A4=44
  • D=187
SLICEL_F5MUX
  • F=32
  • G=32
  • OUT=32
  • S0=32
SLICEL_F6MUX
  • 0=13
  • 1=13
  • OUT=13
  • S0=13
SLICEL_FFX
  • CE=43
  • CK=145
  • D=145
  • Q=145
  • REV=5
  • SR=118
SLICEL_FFY
  • CE=53
  • CK=179
  • D=179
  • Q=179
  • SR=150
SLICEL_G
  • A1=189
  • A2=127
  • A3=94
  • A4=49
  • D=191
SLICEL_GNDF
  • 0=62
SLICEL_GNDG
  • 0=56
SLICEL_XORF
  • 0=61
  • 1=61
  • O=61
SLICEL_XORG
  • 0=62
  • 1=62
  • O=62
SLICEM
  • BX=38
  • BY=55
  • CE=3
  • CIN=8
  • CLK=56
  • COUT=8
  • F1=40
  • F2=32
  • F3=32
  • F4=31
  • F5=22
  • FX=9
  • FXINA=16
  • FXINB=16
  • G1=58
  • G2=55
  • G3=55
  • G4=50
  • SHIFTIN=10
  • SHIFTOUT=10
  • SR=54
  • X=7
  • XB=13
  • XQ=9
  • Y=25
  • YB=17
  • YQ=7
SLICEM_CYMUXF
  • 0=8
  • 1=8
  • OUT=8
  • S0=8
SLICEM_CYMUXG
  • 0=5
  • 1=8
  • OUT=8
  • S0=8
SLICEM_F
  • A1=40
  • A2=32
  • A3=32
  • A4=31
  • D=46
  • DI=31
  • WS=31
SLICEM_F5MUX
  • F=27
  • G=27
  • OUT=27
  • S0=27
SLICEM_F6MUX
  • 0=16
  • 1=16
  • OUT=16
  • S0=16
SLICEM_FFX
  • CE=3
  • CK=9
  • D=9
  • Q=9
  • SR=5
SLICEM_FFY
  • CK=7
  • D=7
  • Q=7
SLICEM_FMC15_BLACKBOX
  • MC15=23
  • WS2=23
SLICEM_G
  • A1=58
  • A2=55
  • A3=55
  • A4=50
  • D=57
  • DI=49
  • WS=49
SLICEM_GMC15_BLACKBOX
  • MC15=42
  • WS2=42
SLICEM_GNDF
  • 0=8
SLICEM_GNDG
  • 0=5
SLICEM_VDDG
  • 1=3
SLICEM_WSGEN
  • CK=49
  • WE=49
  • WSF=31
  • WSG=49
SLICEM_XORF
  • 0=5
  • 1=5
  • O=5
SLICEM_YBUSED
  • 0=17
  • OUT=17
 
Tool Usage
Command Line History
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s700a-fg484-5 -cm area -pr b -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 5 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
XSLTProcess 133 133 0 0 0 0 0
_impact 19 14 0 0 0 0 0
_xps 1 1 0 0 0 0 0
arwz 43 43 0 0 0 0 0
bitgen 59 59 0 0 0 0 0
cpldfit 133 133 0 0 0 0 0
hprep6 81 81 0 0 0 0 0
ibiswriter 4 4 0 0 0 0 0
map 109 98 0 0 0 0 0
netgen 23 20 0 0 0 0 0
ngcbuild 4 4 0 0 0 0 0
ngdbuild 255 254 0 0 0 0 0
par 93 74 19 0 0 0 0
platgen 2 0 0 0 0 0 0
reportgen 5 5 0 0 0 0 0
taengine 97 96 0 0 0 0 0
trce 76 75 0 0 0 0 0
tsim 100 99 0 0 0 0 0
xbash 8 8 0 0 0 0 0
xpwr 3 3 0 0 0 0 0
xst 346 346 0 0 0 0 0
 
Help Statistics
Search words with results
BUFGCTRL ( 1 )
Help files
/doc/japanese/books/manuals.pdf ( 1 ) /doc/japanese/isehelp/ise_c_language_templates.htm ( 1 )
/doc/japanese/isehelp/ise_c_overview.htm ( 1 ) /doc/japanese/isehelp/ise_r_comp_gck_gts_gsr.htm ( 1 )
/doc/japanese/isehelp/ise_r_comp_global_buffers.htm ( 1 ) /doc/japanese/isehelp/ite_c_overview.htm ( 1 )
/doc/japanese/wizards/arwz/awz_db_dcmgen.htm ( 1 )
 
Project Statistics
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_Simulator=ISE Simulator (VHDL/Verilog)
PROP_Top_Level_Module_Type=HDL PROP_PreferredLanguage=Verilog
PROP_Enable_Message_Filtering=false PROP_Enable_Incremental_Messaging=false
PROP_UseSmartGuide=false Partitions count=1
FILE_CDC=1 FILE_TBW=1
FILE_UCF=1 FILE_VERILOG=3
FILE_XAW=1 PROP_DevDevice=xc3s700a
PROP_DevFamily=Spartan3A and Spartan3AN PROP_DevPackage=fg484
PROP_FitterReportFormat=HTML PROP_PreTrceFastPath=true
PROP_netgenRenameTopLevEntTo=Demo_Top PROP_UserConstraintEditorPreference=Constraints Editor
PROP_parGenAsyDlyRpt=true PROP_parGenClkRegionRpt=true
PROP_xilxMapPackRegInto=For Inputs and Outputs PROP_xilxPostTrceRpt=Error Report
PROP_xilxPreTrceRpt=Error Report Project duration(days)=
 
Core Statistics
Core Type=chipscope_icon_v1_02_a
c_build_revision=1 c_core_major_ver=1 c_core_minor_alpha_ver=97 c_core_minor_ver=2
c_core_type=1 c_major_version=10 c_mfg_id=1 c_minor_version=1
c_num_control_ports=1 c_use_control0=1 c_use_control1=0 c_use_control10=0
c_use_control11=0 c_use_control12=0 c_use_control13=0 c_use_control14=0
c_use_control2=0 c_use_control3=0 c_use_control4=0 c_use_control5=0
c_use_control6=0 c_use_control7=0 c_use_control8=0 c_use_control9=0
c_use_ext_bscan=0 c_use_jtag_bufg=1 c_use_unused_bscan=0 c_user_scan_chain=1
c_xdevicefamily=spartan3a
Core Type=chipscope_ila_v1_02_a
c_build_revision=1 c_core_major_ver=1 c_core_minor_alpha_ver=97 c_core_minor_ver=2
c_core_type=2 c_data_depth=512 c_data_width=1 c_ext_cap_pin_mode=0
c_ext_cap_rate_mode=0 c_ext_cap_use_reg=1 c_m0_tpid=0 c_m0_type=1
c_m10_tpid=10 c_m10_type=0 c_m11_tpid=11 c_m11_type=0
c_m12_tpid=12 c_m12_type=0 c_m13_tpid=13 c_m13_type=0
c_m14_tpid=14 c_m14_type=0 c_m15_tpid=15 c_m15_type=0
c_m1_tpid=1 c_m1_type=0 c_m2_tpid=2 c_m2_type=0
c_m3_tpid=3 c_m3_type=0 c_m4_tpid=4 c_m4_type=0
c_m5_tpid=5 c_m5_type=0 c_m6_tpid=6 c_m6_type=0
c_m7_tpid=7 c_m7_type=0 c_m8_tpid=8 c_m8_type=0
c_m9_tpid=9 c_m9_type=0 c_major_version=10 c_mcnt0_width=1
c_mcnt10_width=1 c_mcnt11_width=1 c_mcnt12_width=1 c_mcnt13_width=1
c_mcnt14_width=1 c_mcnt15_width=1 c_mcnt1_width=1 c_mcnt2_width=1
c_mcnt3_width=1 c_mcnt4_width=1 c_mcnt5_width=1 c_mcnt6_width=1
c_mcnt7_width=1 c_mcnt8_width=1 c_mcnt9_width=1 c_mfg_id=1
c_minor_version=1 c_num_ext_cap_pins=8 c_num_match_units=2 c_num_tseq_cnt=0
c_num_tseq_states=16 c_ram_type=1 c_srl16_type=2 c_tc_mcnt_width=1
c_timestamp_depth=512 c_timestamp_type=0 c_timestamp_width=32 c_trig0_width=1
c_trig10_width=1 c_trig11_width=1 c_trig12_width=1 c_trig13_width=1
c_trig14_width=1 c_trig15_width=1 c_trig1_width=8 c_trig2_width=1
c_trig3_width=1 c_trig4_width=1 c_trig5_width=1 c_trig6_width=1
c_trig7_width=1 c_trig8_width=1 c_trig9_width=1 c_tseq_cnt0_width=1
c_tseq_cnt1_width=1 c_tseq_type=1 c_use_atc_clkin=0 c_use_data=0
c_use_gap=0 c_use_inv_clk=0 c_use_mcnt0=0 c_use_mcnt1=0
c_use_mcnt10=0 c_use_mcnt11=0 c_use_mcnt12=0 c_use_mcnt13=0
c_use_mcnt14=0 c_use_mcnt15=0 c_use_mcnt2=0 c_use_mcnt3=0
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c_use_mcnt8=0 c_use_mcnt9=0 c_use_rpm=1 c_use_storage_qual=1
c_use_tc_mcnt=0 c_use_trig0=1 c_use_trig1=1 c_use_trig10=0
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c_use_trig9=0 c_use_trig_out=0 c_use_trigdata0=1 c_use_trigdata1=1
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c_use_trigdata4=0 c_use_trigdata5=0 c_use_trigdata6=0 c_use_trigdata7=0
c_use_trigdata8=0 c_use_trigdata9=0 c_xdevicefamily=spartan3a