FPGA_EDIT Project Status (05/09/2008 - 18:22:38) | |||
Project File: | FPGA_EDIT.ise | Current State: | Bitgen Completed |
Module Name: | EDIT_Top |
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No Errors |
Target Device: | xc3s500e-4fg320 |
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No Warnings |
Product Version: | ISE 10.1.01 - Foundation |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Timing Report) |
FPGA_EDIT Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 29 | 9,312 | 1% | ||
Number of 4 input LUTs | 12 | 9,312 | 1% | ||
Logic Distribution | |||||
Number of occupied Slices | 24 | 4,656 | 1% | ||
Number of Slices containing only related logic | 24 | 24 | 100% | ||
Number of Slices containing unrelated logic | 0 | 24 | 0% | ||
Total Number of 4 input LUTs | 43 | 9,312 | 1% | ||
Number used as logic | 12 | ||||
Number used as a route-thru | 31 | ||||
Number of bonded IOBs | 6 | 232 | 2% | ||
Number of BUFGMUXs | 1 | 24 | 4% |
Performance Summary | [-] | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | 金 5 9 17:30:29 2008 | 0 | 0 | 0 | |
Translation Report | Current | 金 5 9 17:30:38 2008 | 0 | 0 | 0 | |
Map Report | Current | 金 5 9 17:30:48 2008 | 0 | 0 | 4 Infos | |
Place and Route Report | Current | 金 5 9 17:31:09 2008 | 0 | 0 | 2 Infos | |
Static Timing Report | Current | 金 5 9 17:31:16 2008 | 0 | 0 | 3 Infos | |
Bitgen Report | Current | 金 5 9 18:22:38 2008 | X 2 Errors | 0 | 0 |