FPGA_EDIT Project Status (05/09/2008 - 18:22:38)
Project File: FPGA_EDIT.ise Current State: Bitgen Completed
Module Name: EDIT_Top
  • Errors:
No Errors
Target Device: xc3s500e-4fg320
  • Warnings:
No Warnings
Product Version: ISE 10.1.01 - Foundation
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
FPGA_EDIT Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 29 9,312 1%  
Number of 4 input LUTs 12 9,312 1%  
Logic Distribution     
Number of occupied Slices 24 4,656 1%  
    Number of Slices containing only related logic 24 24 100%  
    Number of Slices containing unrelated logic 0 24 0%  
Total Number of 4 input LUTs 43 9,312 1%  
    Number used as logic 12      
    Number used as a route-thru 31      
Number of bonded IOBs 6 232 2%  
Number of BUFGMUXs 1 24 4%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent金 5 9 17:30:29 2008000
Translation ReportCurrent金 5 9 17:30:38 2008000
Map ReportCurrent金 5 9 17:30:48 2008004 Infos
Place and Route ReportCurrent金 5 9 17:31:09 2008002 Infos
Static Timing ReportCurrent金 5 9 17:31:16 2008003 Infos
Bitgen ReportCurrent金 5 9 18:22:38 2008X 2 Errors00

Date Generated: 05/09/2008 - 18:22:39
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