`define ID_A 8'h11
`define ID_B 8'hA0
`define ID_C 8'h5D

parameter [1:0]
ID_IDLE = 2'b00,
ID_S_BIT = 2'b01,

ID_BIT_01 = 2'b10;

integer temp1,temp2;

r回頁首

Assign 　的　語　法

assign Z1 = TX1 | RX1;
assign Z2 = TX2 | RX2;

assign Z1_1 = JP1_1?(1'b0):(JP1_2?1'b0:1'b1);
assign Z1_2 = JP1_1?(JP1_2?1'b0:1'b1):(1'b0);

r回頁首

always @ (  posedge CLK  )
begin
if( CNT == 4 )
CNT<= 3'b000;
else
CNT<= CNT + 3'b001;
end

always @ (  negedge CLK )
begin
if( CNT1 == 4 )
CNT1<= 3'b000;
else
CNT1<= CNT1 + 3'b001;
end

r回頁首

Case　的　語　法

always
begin
case (CLK_JANET)
4'b0000: begin STATE_JENNY <= 4'b0001; end
4'b0001: begin STATE_JENNY <= 4'b0010; end
4'b0010: begin STATE_JENNY <= 4'b0011; end
4'b0011: begin STATE_JENNY <= 4'b0100; end
4'b0100: begin STATE_JENNY <= 4'b0101; end
4'b0101: begin STATE_JENNY <= 4'b0110; end
4'b0110: begin STATE_JENNY <= 4'b0111; end
4'b0111: begin STATE_JENNY <= 4'b0000; end
default : STATE_JENNY <= 4'b0000;
endcase
end
　

r回頁首

always@(control or st or rd or cs or reset)
begin

if(reset == 1'b1)

begin data=4'b0000; end

else if(reset == 1'b0)
　　　begin
　　　　　if(control == 1'b0)
　　　　　　begin
　　　　　　　if(st)　begin 　data=int0; 　end
　　　　　　　else if (!st)　begin 　data=int1;　end
　　　　　　end
　　　　　　else if(control == 1'b1)　begin　data=4'bZZZZ;　end
　　end
end

r回頁首

module CD_4017( CLOCK_CD4017,RESET_CD4017,
// INHIBIT_CD4017,
COUNTER_CD4017,
// CARRY_OUT_CD4017,
COUNTER_BIT,
);

//------------- CD4017 INPUT/OUTPUT/REG --------------------------

input CLOCK_CD4017;
input RESET_CD4017;
//input INHIBIT_CD4017;
//output CARRY_OUT_CD4017;
output [3:0] COUNTER_CD4017;
//reg CARRY_OUT_CD4017;
reg [3:0] COUNTER_CD4017;
reg EN;
output [9:0] COUNTER_BIT;

//\\//\\//\\//\\//\\//\\//\\////\\//\\//\\//\\//\\//\\//\\////\
//------------------------------------------- CD4017 -----------

always @ (posedge CLOCK_CD4017)
begin
if( !RESET_CD4017 ) begin COUNTER_CD4017 <= 4'b0; EN<= 1'b1; end
else
begin
if( COUNTER_CD4017 <= 4'b1000 ) begin
EN<= 1'b0;
COUNTER_CD4017 <= COUNTER_CD4017 + 8'b00000001;
end
else
begin
COUNTER_CD4017 <= 4'b0;
EN<= 1'b0;
end
end
end
/\\//\\//\\//\\//\\//\\//\\////\\//\\//\\//\\//\\//\\//\\////\\/
assign COUNTER_BIT[0] = (COUNTER_CD4017==0 && !EN )?1'b1:1'b0;
assign COUNTER_BIT[1] = (COUNTER_CD4017==1 && !EN )?1'b1:1'b0;
assign COUNTER_BIT[2] = (COUNTER_CD4017==2 && !EN )?1'b1:1'b0;
assign COUNTER_BIT[3] = (COUNTER_CD4017==3 && !EN )?1'b1:1'b0;
assign COUNTER_BIT[4] = (COUNTER_CD4017==4 && !EN )?1'b1:1'b0;
assign COUNTER_BIT[5] = (COUNTER_CD4017==5 && !EN )?1'b1:1'b0;
assign COUNTER_BIT[6] = (COUNTER_CD4017==6 && !EN )?1'b1:1'b0;
assign COUNTER_BIT[7] = (COUNTER_CD4017==7 && !EN )?1'b1:1'b0;

//---------------------------------------------------------------

endmodule
　

r回頁首

module DIV( A_IN,A_OUT,SEL,CNT,CNT1,TT,AOUT,AOUT1);

input A_IN;
input [4:0] SEL;
output A_OUT,AOUT,AOUT1;
output [4:0] CNT,CNT1;
reg [4:0] CNT,CNT1;
reg AOUT,AOUT1;
//***************************************
output [3:0] TT;
reg [3:0] TT;

integer temp1;
//***************************************
always@(posedge A_IN)
begin
temp1 = TT /2;
end
//***************************************
always @ ( posedge A_IN )
begin
if( CNT == SEL-1 )
CNT<= 5'b00000;
else
CNT<= CNT + 5'b00001;
end
//***************************************
always @ ( negedge A_IN )
begin
if( CNT1 == SEL-1 )
CNT1<= 5'b00000;
else
CNT1<= CNT1 + 5'b00001;
end
//***************************************
always @ (CNT or CNT1)
begin
if (CNT == 5'b00000)
AOUT <= 1'b1;
else if(CNT1 == temp1+1 )
AOUT <= 1'b0;
else
AOUT <= AOUT;
end
//***************************************
always @ (CNT)
begin
if (CNT == 5'b00000)
AOUT1 <= 1'b1;
else if(CNT == temp1 )
AOUT1 <= 1'b0;
else
AOUT1 <= AOUT1;
end
//***************************************
always@(posedge A_IN)
begin
case (SEL)
4'b0000: TT <= 4'b0000; //0
4'b0001: TT <= 4'b0001; //01
4'b0010: TT <= 4'b0010; //02
4'b0011: TT <= 4'b0011; //03
4'b0100: TT <= 4'b0100; //04
4'b0101: TT <= 4'b0101; //05
4'b0110: TT <= 4'b0110; //06
4'b0111: TT <= 4'b0111; //07
4'b1000: TT <= 4'b1000; //08
4'b1001: TT <= 4'b1001; //09
4'b1010: TT <= 4'b1010; //10
4'b1011: TT <= 4'b1011; //11
4'b1100: TT <= 4'b1100; //12
4'b1101: TT <= 4'b1101; //13
4'b1110: TT <= 4'b1110; //14
4'b1111: TT <= 4'b1111; //15
default: ;
endcase
end
//***************************************
assign A_OUT = (SEL[0])? AOUT:AOUT1;

endmodule
　

r回頁首

assign DATA_BUS = (EN) ? DATA_OUT : 4'bz;
assign DATA_IN = (!EN) ? DATA_BUS : DATA_IN ;

r回頁首