@
Xilinx s iMPACT Program FPGA & ROM t >> ‰ñŽå‘Išd <<
![]() |
iMPACT @ @œ@iMPACT ¥ˆê“…“‹”z XILINX ISE ŠJᢓîé“內Œš“Ià–錄 CPLD/FPGA “I“îé“ @œ@i“üŽåá`–ÊŽž˜ð—L™_ŒÂŽå—vŽ‹âx•ª•Ê¥ y Flows z , y iMPACT Processes z @œ@”‡™_ŒÂŽ‹âxäoISE’†“I y Source z , y Processes zˆêžé,“s—L›”œä“IèŒW @ @ |
@
![]() |
@ @”@‰½ŠJ啟 iMPACT @œ@‰Â“§‰ßISE“I“îé“‘ÅŠJ.ˆê”Ê›€“I‘I€“sImplement Design‰º–Ê @œ@另ŠO–ç‰ÂˆÈ—˜—p’öŽ®W’†“I´šdÝISE“IˆÀåä–Ú錄‰ºQ“ž”‡ŒÂ‘I€(”@š¤Ž¦)
@ |
@
![]() |
@ @•àé…(1) @ @œ@‘ÅŠJiMPACTŒã’öŽ®˜ðŽ©“®Ž·s Boundary Scan ,”@‰Ê–Ú‘Odé““s›ßãS€”õD“I‰º,˜ðèûަJTEG Chain㊗L“IDevice @œ@”@‰Ê¥šdàÕŠJ啟iMPACT,˜ð—LˆêŒÂŽ‹âxæm–⥕s¥—vÚ“üProject.....”‡Žž你‰ÂˆÈ‘I¢—ª‰ßˆ½¥Žw’èProject˜Hœl @ @ |
@
![]() |
@ @•àé…(2) @ @œ@‘æˆêŽŸŠJ啟Žž,”@‰Êdé““s›ßãSåä’uD( ‘œ“dŒ¹,Cable”V—Þ“I.... )˜ðèûަ—ÞŽ—ã–Êš¤Ž¦“Iá`–Ê @ @ |
@
![]() |
@ @•àé…(3) @ @œ@Ú’˜˜ð—v你‘I¢檔ˆÄ @œ@FPGA << ˜ðŽù—vBIT檔..à–錄Œã˜ðdVRESET,è“dŒãCODEA•s‘¶Ý—¹A¥SRAM @œ@CPLD << ˜ðŽù—vJED檔,à–錄Œãè“dŠÒ˜ð‘¶Ý @œ@Xilinx PROM & SPI Flash << ”‡ŒÂŽù—vMCS檔ˆÄ ?? ”@‰½»ìMCS檔ˆÄ @ @@‚w‚h‚k‚h‚m‚w@‚o‚q‚n‚l “Imcs檔ˆÄ•sŽx‰‡‚w‚h‚k‚h‚m‚w 3rd SPI Flash“Imcs檔ˆÄ @ @ |
@
![]() |
@ @•àé…(4) @ @œ@ác‘I¢Ž‹âxŒ‹‘©Œã..˜ðoŒ»”‡ŒÂ›”œä“Iá`–Ê @ |
@
![]() |
@ @•àé…(5) @ @œ@—pŠŠ‘lêyˆê‰ºDevice,˜ðoŒ»Œ÷”\Ž‹âx,‰ä˜ìí—p“IŽw—ß”@‰º @1. Program @ 2. Erase@ @ @ |
@
![]() |
@ @•àé…(6) @ @œ@Ž·s”C‰½Žw—ß..”@‰Ê¬Œ÷˜ð‘i你Š®¬.....”@‰Ê...Ÿ“¬Œ÷A˜ðèûަ‰ºš¤“I”Í—á@. @ |
@
@
![]() |
@ @•àé…(7) @ @”@š¤Ž¦ < 1 >•\ަ޷s“IŽw—߬Œ÷ < 2 >•\ަŸ“¬Œ÷....”‡Žž‰ÂˆÈCHECK Console <3> “IŽ‹âx.ŠÅ哪ŒÂ’n•ûo—¹–â‘è..... @ @ |
@
@ @----@˜@iMPACT Program FPGA & ROM@---- @----@˜@Generate PROM MCS File@---- @----@˜@Generate 3rd SPI MCS File@---- @----@˜@iMPACT Program ‚R‚’‚„ SPI Flash@---- @----@˜@FPGA Program SPI Flas‚ˆ@---- @ |
@